Part 1 must be in the approved Form C. Part 2 consists of the terms and conditions normally associated with the type of general instrument being registered and may be:. Below the heading, it is not necessary to recite the parties. The express terms may begin with the recitals, if any. Era uma maravilha poder armazenar os programas na fitas sim, ele usava fitas desse computador. Quando o Dr.
Lotze escreveu um pequeno montador em Basic, o trabalho decolou. Em ,. Esperamos que o nosso leitor receba um produto de excelente qualidade. O Mercado de Microcontroladores Arquitetura von Newmann Versus Arquitetura de Harvard A RAM Interna Palavra de Estado do Programa Soma de 8 Bits Soma de 8 Bits com Carry Incremento de 8 Bits Decremento de 8 Bits Incremento de 16 Bits Ajuste Decimal AND de 8 Bits OR de 8 Bits XOR de 8 Bits Ativar, Zerar ou Complementar um Bit Desvios Baseados em Bits Saltos Incondicionais Saltos Condicionais Chamadas de Subrotinas Retorno das Subrotinas Uso da Pilha Escrevendo Programas para ASM Controles do Montador Diretivas do Montador Uso do Montador ASM O Processador de Macros A Porta P Escrita nas Portas Leitura das Portas Detalhes sobre o Emprego de Portas Conceitos sobre os Contadores e Temporizadores Registradores Envolvidos Modo Modo Passo a Passo A Porta Serial do PC Ciclos de Barramento Portas e Ciclos de Barramento Barramentos para o Plantas do Pentacontrolador Plata 1: CPU Planta 3: Decodificador Planta 4: LEDs Planta 5: LCD Planta 6: Teclado Planta 9: Infravermelho Planta Interface IrDA Planta USB Planta Desacoplamento O Programa de Boot O Programa P5C.
Controle do Fluxo de Programa Ponteiros e Vetores Particularidades do SDCC para Classes de Armazenamento A Rotina de Partida Pinagem dos Mostradores LCD Formato do LCD Controle de Acesso ao LCD Reset do Mostrador LCD Interface com Mostradores LCD Conector do Teclado Comandos Enviados para o Teclado Comandos Enviados pelo Teclado DS89C Dalas - Maxim Anexo Montagem do Pentacontrolador Em seguida, abordaremos de maneira breve o mercado de microcontroladores, indicando os principais fabricantes.
Para tornar bem claro o conceito de microcontrolador, consideremos o projeto de um sistema bem simples, por exemplo, o controlador para um elevador.
O que tal processador deveria controlar? Com o intuito de fazer tudo isso, propomos a arquitetura da figura 1. Arquitetura para o controlador de um elevador. Essa porta paralela ainda serve para comandar o painel e acender luzes de alerta. Usando a. Portanto, para executar uma tarefa simples como a de controlar um elevador, chegamos facilmente a um sistema com um total de 6 ou 7 circuitos integrados CI.
Mas que vantagens haveria ao colocar todos aqueles blocos da figura 1. O diagrama de figura 1. A figura 1. RAM interna com bytes dedicados aos registradores especiais. RAM interna com bytes para uso do programador. Porta Serial bidirecional. A figura 2. Devemos notar que a arquitetura da figura 2. A Figura 2. Nessa arquitetura da Figura 2. Figura 2. Microprocessador empregando a arquitetura de Harvard. RD ler WR escrever. Convertendo arquitetura de Harvard em arquitetura von Neuman.
Tabela 2. Para tais tarefas, o tamanho da RAM interna pode ser suficiente. Isto facilita e barateia o projeto. A arquitetura disponibiliza ao programador 4 conjuntos de registradores, sendo que cada conjunto recebe o nome de Banco de Registradores. O programador pode escolher, a qualquer instante, qual banco deseja usar. Um pouco mais adiante, veremos que existem dois bits, denominados RS1 e RS0, onde o programador indica qual banco deve estar ativo. Para salvar ou recuperar seu contexto, cada subrotina necessita apenas de mudar o banco de registradores.
Assim, um byte igual a 7AH tem seu bit 0 igual a 0, seu bit 3 igual a 1 e seu bit 7 igual a 0. Assim, o bit 20H. Ainda na figura 2. TCON, P0. Mais adiante, veremos que o fato de podermos acessar diretamente os bits desses registradores facilita muito o controle dos recursos do processador.
Assim o bit P0. O mapeamento dos bits pertencentes aos registradores SFR. Esse registrador, apresentado na figura 2. Tabela 3. Velocidade Tamanho Tempo de Qtd. Ao estudarmos a tabela 3. Ri Qualquer um dos registradores: R0, R1.
A Acumulador. Notar que Rn representa um dos 8 registradores R0, R1, For example, compensating for known temperature variations in key laser characteristics such as slope efficiency. Monitoring functions. Monitoring various parameters related to the transceiver operating characteristics and environment.
Examples of parameters that it would be desirable to monitor include laser bias current, laser output power, receiver power levels, supply voltage and temperature. Ideally, these parameters should be monitored and reported to, or made available to, a host device and thus to the user of the transceiver. Power on time. It would be desirable for the transceiver's control circuitry to keep track of the total number of hours the transceiver has been in the power on state, and to report or make this time value available to a host device.
Other digital signals. It would be desirable to enable a host device to be able to configure the transceiver so as to make it compatible with various requirements for the polarity and output types of digital inputs and outputs. For instance, digital inputs are used for transmitter disable and rate selection functions while outputs are used to indicate transmitter fault and loss of signal conditions.
The configuration values would determine the polarity of one or more of the binary input and output signals. In some transceivers it would be desirable to use the configuration values to specify the scale of one or more of the digital input or output values, for instance by specifying a scaling factor to be used in conjunction with the digital input or output value. Few if any of these additional functions are implemented in most transceivers, in part because of the cost of doing so.
Some of these functions have been implemented using discrete circuitry, for example using a general purpose EEPROM for identification purposes, by inclusion of some functions within the laser driver or receiver circuitry for example some degree of temperature compensation in a laser driver circuit or with the use of a commercial micro-controller integrated circuit.
However, to date there have not been any transceivers that provide a uniform device architecture that will support all of these functions, as well as additional functions not listed here, in a cost effective manner. It is the purpose of the present invention to provide a general and flexible integrated circuit that accomplishes all or any subset of the above functionality using a straightforward memory mapped architecture and a simple serial communication mechanism.
The main circuit [] 1 contains at a minimum transmit and receiver circuit paths and power 19 and ground connections The receiver circuit typically consists of a Receiver Optical Subassembly ROSA 2 which contains a mechanical fiber receptacle as well as a photodiode and pre-amplifier preamp circuit.
The postamp circuit also often provides a digital output signal known as Signal Detect or Loss of Signal indicating the presence or absence of suitably strong optical input.
The Signal Detect output is provided as an output on pin The laser driver circuit will typically provide AC drive and DC bias current to the laser. Typically, the laser driver circuitry will require individual factory setup of certain parameters such as the bias current or output power level and AC modulation drive to the laser.
Typically this is accomplished by adjusting variable resistors or placing factory selected resistors 7 , 9 i. Additionally, temperature compensation of the bias current and modulation is often required. This function can be integrated in the laser driver integrated circuit or accomplished through the use of external temperature sensitive elements such as thermistors 6 , 8. In addition to the most basic functions described above, some transceiver platform standards involve additional functionality.
In the GBIC standard, the TX disable pin allows the transmitter to be shut off by the host device, while the TX fault pin is an indicator to the host device of some fault condition existing in the laser or associated laser driver circuit. In addition to this basic description, the GBIC standard includes a series of timing diagrams describing how these controls function and interact with each other to implement reset operations and other actions. Most of this functionality is aimed at preventing non-eyesafe emission levels when a fault conditions exists in the laser circuit.
These functions may be integrated into the laser driver circuit itself or in an optional additional integrated circuit As an alternative to mechanical fiber receptacles, some prior art transceivers use fiber optic pigtails which are standard, male fiber optic connectors. Similar principles clearly apply to fiber optic transmitters or receivers that only implement half of the full transceiver functions.
The present invention is preferably implemented as a single-chip integrated circuit, sometimes called a controller, for controlling a transceiver having a laser transmitter and a photodiode receiver. In some embodiments the controller further includes a cumulative clock for generating a time value corresponding to cumulative operation time of the transceiver, wherein the generated time value is readable via the serial interface.
In some embodiments the controller further includes a power supply voltage sensor that generates a power level signal corresponding to a power supply voltage level of the transceiver. In these embodiments the analog to digital conversion circuitry is configured to convert the power level signal into a digital power level value and to store the digital power level value in a predefined power level location within the memory.
Further, the comparison logic of the controller may optionally include logic for comparing the digital power level value with a power i. It is noted that the power supply voltage sensor measures the transceiver voltage supply level, which is distinct from the power level of the received optical signal.
In some embodiments the controller further includes a temperature sensor that generates a temperature signal corresponding to a temperature of the transceiver. In these embodiments the analog to digital conversion circuitry is configured to convert the temperature signal into a digital temperature value and to store the digital temperature value in a predefined temperature location within the memory. Further, the comparison logic of the controller may optionally include logic for comparing the digital temperature value with a temperature limit value, generating a flag value based on the comparison of the digital temperature signal with the temperature limit value, and storing a temperature flag value in a predefined temperature flag location within the memory.
Additional objects and features of the invention will be more readily apparent from the following detailed description and appended claims when taken in conjunction with the drawings, in which: []. A transceiver [] based on the present invention is shown in FIGS. The transceiver contains a Receiver Optical Subassembly ROSA and Transmitter Optical Subassembly TOSA along with associated post-amplifier and laser driver integrated circuits that communicate the high speed electrical signals to the outside world.
In this case, however, all other control and setup functions are implemented with a third single-chip integrated circuit called the controller IC. The controller IC [] handles all low speed communications with the end user. The controller IC has a two wire serial interface , also called the memory interface, for accessing memory mapped locations in the controller.
Memory Map Tables 1 , 2 , 3 and 4 , below, are an exemplary memory map for one embodiment of a transceiver controller, as implemented in one embodiment of the present invention. It is noted that Memory Map Tables 1 , 2 , 3 and 4 , in addition to showing a memory map of values and control features described in this document, also show a number of parameters and control mechanisms that are outside the scope of this document and thus are not part of the present invention.
In the preferred embodiment, the serial interface operates in accordance with the two wire serial interface standard that is also used in the GBIC and SFP standards, however other serial interfaces could equally well be used in alternate embodiments. The two wire serial interface is used for all setup and querying of the controller IC , and enables access to the optoelectronic transceiver's control circuitry as a memory mapped device.
That is, tables and parameters are set up by writing values to predefined memory locations of one or more nonvolatile memory devices , , e. This technique is consistent with currently defined serial ID functionality of many transceivers where a two wire serial interface is used to read out identification and capability data stored in EEPROM. It is noted here that some of the memory locations in the memory devices [] , , are dual ported, or even triple ported in some instances.
That is, while these memory mapped locations can be read and in some cases written via the serial interface , they are also directly accessed by other circuitry in the controller Similarly, there are flags stored memory that are A written by logic circuit , and B read directly by logic circuit An example of a memory mapped location not in memory devices but that is effectively dual ported is the output or result register of clock In this case the accumulated time value in the register is readable via the serial interface , but is written by circuitry in the clock circuit In addition to the result register of the clock [] , other memory mapped locations in the controller may be implemented as registers at the input or output of respective sub-circuits of the controller.
For instance, the margining values used to control the operation of logic may be stored in registers in or near logic instead of being stored within memory device In another example, measurement values generated by the ADC may be stored in registers.
The memory interface is configured to enable the memory interface to access each of these registers whenever the memory interface receives a command to access the data stored at the corresponding predefined memory mapped location.
In an alternate embodiment, the time value in the result register of the clock [] , or a value corresponding to that time value, is periodically stored in a memory location with the memory e.
In this alternate embodiment, the time value read by the host device via interface is the last time value stored into the memory , as opposed to the current time value in the result register of the clock As shown in FIGS. These connections serve multiple functions. In a preferred embodiment, the controller [] includes mechanisms to compensate for temperature dependent characteristics of the laser.
This is implemented in the controller through the use of temperature lookup tables that are used to assign values to the control outputs as a finction of the temperature measured by a temperature sensor within the controller IC It should also be noted that while FIG.
In addition to temperature dependent analog output controls, the controller IC may be equipped with a multiplicity of temperature independent one memory set value analog outputs. These temperature independent outputs serve numerous functions, but one particularly interesting application is as a fine adjustment to other settings of the laser driver [] or postamp in order to compensate for process induced variations in the characteristics of those devices.
One example of this might be the output swing of the receiver postamp Normally such a parameter would be fixed at design time to a desired value through the use of a set resistor. It often turns out, however, that normal process variations associated with the fabrication of the postamp integrated circuit induce undesirable variations in the resulting output swing with a fixed set resistor.
In addition to the connection from the controller to the laser driver [] , FIG. These are analog monitoring connections that the controller IC uses to provide diagnostic feedback to the host device via memory mapped locations in the controller IC. The controller IC in the preferred embodiment has a multiplicity of analog inputs.
These analog signals are scanned by a multiplexer and converted using an analog to digital converter ADC The ADC has 12 bit resolution in the preferred embodiment, although ADC's with other resolution levels may be used in other embodiments. The converted values are stored in predefined memory locations, for instance in the diagnostic value and flag storage device shown in FIG.
These values are calibrated to standard units such as millivolts or microwatts as part of a factory calibration procedure. The digitized quantities stored in memory mapped locations within the controller IC include, but are not limited to, the laser bias current, transmitted laser power, and received power as measured by the photodiode detector in the ROSA [] In the memory map tables e.
The memory map tables indicate the memory locations where, in an exemplary implementation, these measured values are stored, and also show where the corresponding limit values, flag values, and configuration values e. As shown in FIG. An analog voltage level signal generated by this sensor is converted to a digital voltage level signal by the ADC , and the digital voltage level signal is stored in memory Inside this section you can find a complete range of endoscope brushes and a very good selection of endoscope accessories.
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